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Intel i860

Intel's 64-bit RISC microprocessor, marketed as a "supercomputer-on-a-chip," found niche use in parallel supercomputing systems and as an attached processor despite limited adoption in mainstream workstations.

Intel intel-i860, archival photo
Photo: John E. Stone, CC BY-SA 4.0, via Wikimedia Commons. source

The i860 stood as Intel's most aggressive departure from its x86 lineage to date. A 64-bit RISC design explicitly engineered for floating-point dominance in scientific computing7, the processor combined a RISC core with a deeply pipelined floating-point unit and dual instruction mode, enabling concurrent execution of integer and floating-point operations under ideal conditions38. Its architecture followed the Harvard model, featuring separate instruction and data caches to sustain high bandwidth between functional units5.

The original i860 ran at 40 MHz and was rated at up to 80 MFLOPS in single-precision and 60 MFLOPS in double-precision floating-point operations7. Intel claimed the chip's scalar performance surpassed that of a Cray 1 supercomputer, though real-world benchmarks showed it often lagged behind an i486 paired with a Weitek WTL4167 floating-point accelerator in scalar workloads75. Peak performance required careful code optimization to exploit pipelining and parallelism, achievable only through vectorization tools like the 860 Vectorizer, which translated C or FORTRAN into calls against Intel's proprietary vector library of over 400 primitives3. The chip contained a floating-point adder and multiplier, and reportedly integrated 8 KB and 16 KB caches for instructions and data respectively, though one source specifies a 4 KB, 64-bit-wide instruction cache capable of feeding both CPU and FPU simultaneously via independent 32-bit buses75.

The second-generation i860 XP elevated the design with 2.5 million transistors on a single die, operating at 50 MHz and delivering 100 MFLOPS (single-precision) and 75 MFLOPS (double-precision)68. It featured 16 KB instruction and 16 KB data caches and achieved a peak cache bandwidth of 1.2 GB/sec8. This iteration powered the Paragon XP/S and XP/E supercomputers18. Earlier, the iPSC/860 supercomputer relied on the original i860, running the NX/2 operating system on its compute nodes47. The Paragon line later transitioned to OSF/1 as its primary operating environment11.

Despite its technical ambition, the i860 never gained traction as a standalone CPU in workstations. Instead, it served as an attached processor, augmenting SPARC-based systems in specialized markets such as seismic processing and 3D graphics2. The Hauppauge 4860 motherboard, for example, paired an 80486 host CPU with an i860 coprocessor, suggesting a hybrid role where the i860 handled floating-point or graphics tasks35. Software support included the APX (Attached Processor Executive) operating system, the iRMK real-time kernel, and development tools such as the icc compiler and as860 assembler34610. Libraries like BLAS, NAG, and the IMSL/860 port extended its numerical utility73. The iGL graphics pipeline used the chip's built-in graphics hardware for geometry and rendering, a rare integration for a general-purpose microprocessor at the time3.

Intel positioned the i860 as a proving ground for technologies later absorbed into the Pentium line, acknowledging its role as a research vehicle as much as a product2. By 1994, industry observers noted concerns over its long-term viability, speculating that internal resources had shifted decisively toward Pentium development9. While the chip failed to establish a broad market, it found sustained demand in government-funded supercomputing programs, where it was consumed "by the thousands"9. Its legacy lies not in commercial success, but in demonstrating the feasibility of integrating supercomputing-class floating-point performance onto a single silicon die, a milestone in microprocessor architecture, however narrowly applied.

Specifications

Architecture64-bit RISC, Harvard-type with separate instruction and data caches
Model (Gen 1)i860
Clock Speed (Gen 1)40 MHz
Floating-Point Performance (Gen 1)80 MFLOPS single precision, 60 MFLOPS double precision
Transistor Count (Gen 1)Approximately 1 million
Cache (Gen 1)Reportedly 8 KB instruction, 16 KB data; alternatively described as 4 KB instruction cache, 64-bit-wide
Model (Gen 2)i860 XP
Clock Speed (Gen 2)50 MHz
Floating-Point Performance (Gen 2)100 MFLOPS single precision, 75 MFLOPS double precision
Transistor Count (Gen 2)Over 2.5 million
Cache (Gen 2)16 KB instruction, 16 KB data
Cache Bandwidth (Gen 2)1.2 GB/sec peak
Execution ModeDual instruction mode (concurrent RISC and FPU execution)
Software Interfacei860 System Binary Standard (SBS), System V Release 4 ABI

References

  1. 312546-001 Paragon XPS i860 64-Bit Microprocessor Assembler Reference Manual Apr1993 (1993)
  2. SunExpert-v03n08-1992-08 (1992)
  3. 1992 02 BYTE 17-02 Tomorrows Chips (1992)
  4. 312130-001 iPSC 860 C Compiler Users Guide Apr91
  5. 1991 01 BYTE 16-01 1990 BYTE Award of Excellence (1991)
  6. 210620-024 Intel Customer Literature Guide Jul92
  7. iPSC 860 Brochure
  8. Paragon XP S XP E Brochure Oct93
  9. SunExpert-v05n08-1994-08 (1994)
  10. 467231-001 iRMK Kernel Reference Dec90
  11. 312490-001 Paragon OSF1 C Compiler Users Guide Apr1993 (1993)
  12. Deitel - The Design of OS2 1992 (1992)
  13. 82420 PCIset ISA and EISA Bridges Mar93
  14. 313059-001 Paragon System Diagnostic 1.2 Release Notes Mar1994 (1994)