Motorola 68020

Motorola’s first fully 32-bit microprocessor in the 68000 family, introduced in the mid-1980s, featured an internal instruction cache, coprocessor support, and new instructions that enabled high-performance computing in workstations and early Unix systems.

The 68020 marked a definitive break from the hybrid 16/32-bit nature of its predecessors, delivering a true 32-bit implementation of the 68000 architecture with full 32-bit internal and external data paths². It introduced a 256-byte instruction cache, later clarified as a 64-longword instruction buffer (256 bytes), dedicated solely to instructions, a feature absent in the 68000 and 68010¹². This internal cache could be manually disabled via a jumper, a design concession likely intended for debugging or compatibility testing³. The chip employed a three-stage instruction pipeline with overlap, improving throughput over earlier models².

Architecturally, the 68020 extended the instruction set with operations such as CHK.L, CHK2, RTD, MULS.L, DIVS.L, BFFXXX, and EXTB.L⁴⁵. These were directly supported by compilers like MPW Pascal, which included a -MC68020 compiler option to generate optimized code; though this rendered applications incompatible with machines lacking the 68020⁴⁵. Despite these additions, the 68020 maintained upward compatibility with the 68000, allowing legacy code to run without modification⁷.

The processor supported external coprocessors, most notably the 68881 floating-point unit, which provided full IEEE 754-compliant 80-bit floating-point arithmetic including transcendental functions². From the programmer’s perspective, the pair appeared as a single integrated processor². It also supported the 68851 PMMU (Paged Memory Management Unit), enabling demand-paged virtual memory systems¹. The 68020 itself operated in both 24-bit and 32-bit processing modes, offering flexibility during the transition from earlier 68000-based systems¹⁴.

System-level implementations varied. One documented configuration, the Altos 3068EP, included 2 MB of DRAM expandable to 16 MB¹⁵. That system also featured an 8 KB two-way set-associative cache on the processor board, distinct from the internal 256-byte instruction cache¹⁵. Another configuration described a 16 KB board-level cache available for both data and instructions¹. The Altos 3068EP operated with zero wait states when sourcing from cache¹⁵.

Motorola projected shipments of 75,000 units for the year 1985, indicating early commercial momentum⁷. The chip was adopted in several notable systems, including the Sun-3 series¹⁶, HP 9000 Series 200/300 workstations², the Macintosh LC¹⁴, and the Altos 3068EP¹⁵. In HP systems, the 68020 was validated using HP-UX, with engineers conducting instruction integrity and virtual memory capability tests, particularly around instruction continuation after interrupts, and reporting bugs directly to Motorola for correction in subsequent mask revisions². Margin testing on new mask sets included low-voltage and high-temperature stress conditions to improve reliability².

Software environments included UNIX System V Release 2.2¹⁵, Sun systems running Release 4.1¹⁶, and HP-UX². Some systems shipped with minimal software; the Motorola Bug monitor was the only software included with certain 68020-based platforms⁸. Migration between systems was constrained: programs could move between 68020 and 68030 boards due to similar floating-point handling, but not to or from 68040-based systems, which introduced incompatible instructions like move16⁶.

Clock speeds reported in system documentation include 16 MHz¹⁴, 16.67 MHz¹², and 25 MHz¹², though discrepancies (e.g., 16.7 MHz¹⁵ vs. 16.67 MHz) suggest variations across implementations or rounding differences. The lack of a stated original chip price in surviving documentation is notable. Source ³ references a $895 price, but this pertains to the DSI-020 coprocessor board, not the standalone 68020³.

Specifications

References

1. 2537240-0001 68020cpu Dec86
2. HP Journal 1986-09 (1986)
3. 1986 08 BYTE 11-08 Object-Oriented Languages (1986)
4. MPW 3.0 Pascal 1988 (1988)
5. MPW Pascal 3.0 Reference 1988 (1988)
6. 2549448-0001F TI System V Release 3.3.1 Information Apr92
7. 1985 07 BYTE 10-07 Computers and Space (1985)
8. The Rainbow Vol. 05 No. 06 - January 1986 (1986)
9. Programming The M68000 1983 Addison-Wesley Publishing Company (1983)
10. 813-2004-14 CardcageSlotAssignments&BackplaneConfigRevA 29Sep88 (2004)
11. PN 072-0228 Apple Service Technical Procedures Macintosh Family Volume Two-Mar 1992 (1992)
12. Altos 3068EP brochure
13. 800-3805-10 System&NetworkAdministrationRevA 27Mar90